1. Field of the Invention
The present invention relates to a semiconductor circuit that uses a field-effect transistor having spin-dependent transport characteristics, and to a semiconductor device that uses the semiconductor circuit.
2. Description of the Related Art
The development of smaller semiconductor elements in recent years has been accompanied by the problem of increased power consumption due to leak currents that flow through transistors when semiconductor circuits are not operating (during standby). Several circuit techniques have been developed and implemented as measures for addressing this increase in leak currents. Unlike conventional techniques that are aimed at increasing speed merely by reducing the power supply voltage VDD and the threshold voltage VTH of the transistors, these circuit techniques more actively control the power supply voltage VDD and the threshold voltage VTH.
The conventional techniques are described in Japanese Laid-open Patent Application No. 2004-111904 (FIG. 17); Sugahara, S. “Ferromagnet/semiconductor hybrid devices using epitaxial ferromagnetic tunnel junctions-Creation of group IV ferromagnetic semiconductors and application thereof to spin devices,” Japan Science and Technology Agency: Promoting basic research in prioritized research fields-Individual Research (aka: “sakigake”) First Class: Results Report (pp. 48-50, FIGS. 5 and 6); and Sugahara, S., Tanaka, M. “Spin MOSFET and its applications,” The 134th Topical Symposium of the Magnetics Society of Japan, The 22th Symposium of the Magnetic Artificial Structured Thin Film, Physical Properties and Functions Joint Seminar “Present and future of spin electronics,” (pp. 93-100); and other publications.
Specifically, a technique for cutting off electrical power to a circuit that is not in use during a standby state using a plurality of transistors having a plurality of different power supply voltages and threshold voltages is cited as an example of a technique for more actively controlling the power supply voltage VDD and the threshold voltage VTH.
Other examples include a technique for dynamically varying the threshold voltage VTH of a transistor by adjusting the bias voltage applied to a silicon substrate; a technique for dynamically adjusting the power supply voltage VDD during circuit operation; and other techniques. The VDD-hopping technique and other techniques are known as examples of techniques for switching a plurality of power supply voltages during circuit operation.
The threshold voltage VTH of a unipolar transistor (Field-Effect Transistor: FET) is considered to be the gate-source voltage VGS when the drain current ID rapidly increases. There are various methods for extracting the threshold voltage VTH, and these methods conceptually have a relationship such as the one shown in FIG. 1.
Examples of techniques for cutting off electrical power to an unused circuit during a standby state using a plurality of transistors that have different threshold voltages include techniques that use an MTCMOS (Multi-Threshold Voltage CMOS (Complementary Metal Oxide Semiconductor)) and a power gate (power gating). Specifically, a power switch (power switch) is provided to a circuit that has a low threshold voltage, and the power supply to the unused circuit is cut by switching the power switch during standby, and leak currents are thereby reduced. A two-input NAND gate will be used to describe an example. FIG. 2A shows a gate-level circuit symbol of a two-input NAND gate to which a power switch is not provided, and FIG. 2B is a circuit diagram showing the gate shown in FIG. 2A at the transistor level. FIG. 3A shows a gate-level circuit symbol of a two-input NAND gate to which a power switch is provided, and FIG. 3B is a circuit diagram showing the gate shown in FIG. 3A at the transistor level.
In the two-input NAND gate shown in FIGS. 2A and 2B, the use of a transistor having a high threshold voltage VTH is assumed, and a NAND circuit 215 having a high threshold voltage (high VTH) is formed using an NMOS transistor 211 having a high threshold voltage (high threshold voltage VTH) and a PMOS transistor 212 having a high threshold voltage (high VTH). Two inputs A and B are used in the NAND circuit 215, and the output is indicated by the letter Z.
In the two-input NAND gate shown in FIGS. 3A and 3B, the use of a transistor having a low threshold voltage VTH is basically assumed, and a NAND circuit 216 having a low threshold voltage (low VTH) is formed using an NMOS transistor 213 having a low threshold voltage (low threshold voltage VTH) and a PMOS transistor 214 having a low threshold voltage (low VTH). The NMOS transistor 211 having a high threshold voltage (high VTH) is used as the power switch.
In the high-VTH NAND circuit 215 shown in FIG. 2, leak currents are extremely minimal and do not pose a practical problem. However, when each transistor is changed to a low-VTH transistor without modifying the structure of the NAND circuit 215 shown in FIG. 2B, leak currents increase to a level that is problematic to implementation.
In the low-VTH NAND gate having a power switch as shown in FIG. 3, the high-VTH power switch (NMOS transistor 211) is turned on during normal operation, the power switch (NMOS transistor 211) is turned off during standby, and leak currents can thereby be cut off during standby. In the circuit design, the entire circuit is first designed using the high-VTH NAND circuit 215 shown in FIG. 3B. The critical path of the circuit is then determined, and the gate on the critical path is converted to the low-VTH NAND circuit 216 that is capable of high-speed operation. A low-VTH NAND gate having a power switch such as the one shown in FIG. 3 is used at this conversion. During normal operation of the circuit, the power switch (NMOS transistor 211) is turned on to allow high-speed operation, and the power switch (NMOS transistor 211) is turned off during standby, whereby leak currents during standby are reduced.
In the same manner as the example described using the two-input NAND gate, a power switch of the same type as the power switch (NMOS transistor 211) provided on the ground (GND) side is provided also to the power supply voltage VDD, whereby the power supply to the unused circuit block can be cut off during standby, thereby enabling a reduction in leak currents during standby.
A technique that uses a scheme (substrate bias scheme) for adjusting a bias voltage (substrate bias voltage) applied to the silicon substrate of the transistor is cited as an example of a technique for dynamically controlling the threshold voltage VTH of a transistor during normal operation of the circuit. This technique takes advantage of the fact that the threshold voltage VTH is varied when a bias voltage is applied to the silicon substrate of a transistor. The silicon substrate of the transistor is normally connected to the GND, but in the substrate bias scheme, the silicon substrate of the transistor is not connected to the GND, and a potential is applied to the silicon substrate to adjust the threshold voltage VTH of the transistor.
When the substrate bias voltage is increased, the potential difference between the silicon substrate and the drain-source decreases, and the width of the depletion layer under the channel decreases. The value is therefore close to the on state of the transistor, and the threshold voltage VTH of the transistor decreases. A scheme in which a positive voltage (in the case of an NMOS; negative voltage in a PMOS) is applied as the substrate bias voltage to reduce the threshold voltage VTH of the transistor is referred to as a forward bias scheme. Conversely, since the width of the depletion layer under the channel increases when the substrate bias voltage is reduced, the value is therefore close to the off state of the transistor, and the threshold voltage VTH of the transistor increases. A scheme in which a negative voltage (in the case of an NMOS; positive voltage in a PMOS) is applied as the substrate bias voltage to increase the threshold voltage VTH of the transistor is referred to as a back bias scheme.
Leak currents can be prevented from increasing during standby through the dynamic application of the substrate bias schemes described above. For example, leak currents can be significantly reduced by increasing the threshold voltage VTH of the transistor during standby. Furthermore, leak currents during normal operation of the circuit can also be reduced by constantly varying the threshold voltage VTH of the transistor according to the processing load of the circuit, temperature increases, and other conditions.
Leak currents can also be reduced by dynamically controlling the power supply voltage VDD in the same manner as the threshold voltage VTH of the transistor. Leak currents can be reduced by using a plurality of power supply voltages VDD according to the circuit, and dynamically controlling the power supply voltages VDD, and particularly by dynamically reducing the power supply voltage VDD of a circuit that has a low load.
As described above, various measures have been developed for addressing increased power consumption due to increases in leak currents and the like, which are caused by reduced size of semiconductor elements, reduced power supply voltages VDD, and other effects.
However, such problems as those described below are apparent in the schemes for suppressing an increase in power consumption by suppressing an increase in leak currents that flow through transistors during standby according to the conventional techniques described above.
First, in the scheme whereby power switches are used so that a power switch is turned on for high-speed operation during normal operation of the circuit, and the power switch is turned off during standby so as to reduce leak currents during standby, since the circuit is blocked from the power supply voltage during standby, a node that is suspended in the circuit appears and the voltage thereof has a different value than the voltage during normal operation of the circuit. Problems therefore occur in that time is required to return from the standby state to the normal operating state.
Schemes that use a power switch also include a scheme for fixing a blocked power line at another power supply potential. In this scheme, the abovementioned node that is suspended in the circuit is unlikely to occur. However, the newly fixed power supply potential is normally set to the same potential as a power supply potential in the reverse polarity in order to reduce the leak current. For example, using FIG. 3B as an example, the high-VTH NMOS transistor 211 is blocked, and the potential between the NMOS transistors 211 and 213 is the same as the power supply potential shown at the top of FIG. 3B. When the voltage is set in this manner, time is required to return the newly fixed power supply potential to the original power supply potential during the return to the normal operating state. Problems also occur in that a large change in potential is also necessary, and large leak currents flow during the switch from standby to normal operation.
In order to overcome these problems, a scheme referred to as ZSCCMOS (Zigzag Super Cut-off CMOS) or the like has been proposed for switching the power supply potential blocked for each adjacent gate to positive or negative to speed the return from the standby state to the normal operating state. However, this scheme has problems in that an extremely large number of power supply potentials are needed.
Second, in the scheme whereby power switches are used so that a power switch is turned on for high-speed operation during normal operation of the circuit, and the power switch is turned off during standby so as to reduce leak currents during standby, since blocking the power supply has the effect of reducing leak currents during standby, leak currents cannot be reduced in circuit blocks or gates in which the power supply cannot be blocked during standby.
Third, when an excessive negative voltage is applied in the substrate bias scheme of a back bias scheme, the VTH is increased by the application of the negative voltage. Therefore, a state similar to the state that occurs when a negative voltage is applied occurs even when a voltage is not applied to the gate, a leak current occurs at the joint between the drain and the substrate, and a joint leak current component referred to as GIDL (Gate Induced Drain Leakage) increases. This GIDL increases particularly as transistors are reduced in size, and leak-current-reducing effects are impossible to obtain. There is therefore almost no reduction in leak currents even when the substrate bias is optimized.
Fourth, as miniaturization progresses and the gate length decreases, short channel effects also occur with respect to the substrate bias effects, and the change in the VTH is therefore extremely small even when a substrate bias is applied.
Fifth, when an excessive positive voltage is applied in the substrate bias scheme of a forward bias scheme, latch-up occurs, and failure and the like sometimes occur. The reason for this is that the transistor is forced on and is caused to operate as a bipolar transistor.
Sixth, since the oxide film thickness, the amount of doping, and the type of gate electrode must be varied in order to implement a plurality of threshold voltages in a scheme that uses a plurality of transistors having different threshold voltages, a significant process burden is involved. The circuit structure also becomes complex when there is a plurality of threshold voltages, and the circuit also becomes difficult to design.
Seventh, the reduction in power consumption is limited even in a combination of the various conventional low-power schemes described above, a scheme referred to as clock gating for stopping the clock supply to an unused circuit block, and other conventional known low-power schemes. Furthermore, the reduction in power consumption is limited even when these techniques are used in combination with a DVS (Dynamic Voltage Scaling) technique for adaptively varying the power supply voltage and the operating frequency according to load. Particularly as size reduction progresses, adequate effects are not obtained merely by combining the measures described above. The development of a new technique is therefore essential.